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Author Topic: Beginner class D design  (Read 8575 times)

Offline OgreVorbis

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Re: Beginner class D design
« Reply #45 on: February 19, 2019, 1711 UTC »
In order to get clean switching, you really need to hit the gates of SiC fets with 15V or greater.  18-20V seems about optimal, any less and RDSon comes up pretty quick and will deteriorate your efficiency and cause excessive heating.

Also, are your power measurements before or after the lowpass filter?  Without a filter, power is likely to read substantially higher due to large amounts of harmonics, which on conventional class D is going to be quite high.

Not sure what your output transformer looks like, but hopefully the primary is made out of large-ish copper tuning to reduce Q and therefore excessive ringing due to circuit strays.  I would try and do something similar to what is found on solid state VHF PA's where some semirigid line is bent into U shapes and the shields soldered together.  This will also help maintain impedances and keep ringing down.

+-RH

OK, thanks! It is really invaluable having your help, no one around me in my day to day could answer, so I appreciate it.

I am measuring after the lowpass filter. It won't fully work on the 3MHz though which might be contributing to the higher number there.
The wire I am using I believe is 12 AWG silicone stranded wire. It is not a coax. I do have some RG-402 though.
What type of ferrite cores do you use? I suspect my main problem is the core type.

Another thing I am wondering for the future: I have four 1020 cores arranged in a binocular form. My board has space for eight fets even though now I am using only four. When I add the additional ferrite cores I won't have space, so can I stack them so I have four on the bottom and four on top. And then loop the wire through all of them (not sure if I would need to cross over to the opposite top side). I have never seen it done this way.
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Offline redhat

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Re: Beginner class D design
« Reply #46 on: February 19, 2019, 1800 UTC »
I've tried both 43 and 61 material ferrites, not much difference I could note, although with your higher harmonic power I could see some difference in this application, 43 may be better.

I would try something similar to this, wound with coax, shield grounded only on the load end http://www.communication-concepts.com/rf2000-transformer/

+-RH
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Offline Stretchyman

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Re: Beginner class D design
« Reply #47 on: February 19, 2019, 2114 UTC »
Yep You need 12V min on the gates, 15V is optimum for SiC I have found. O/P tran wise check the FAT5 design, I copied that and works a treat. Stack a pair or T200-2's and wind LH CW and the RH CCW, if that makes sense?

Check amfone for the same design of o/p tran.


http://amfone.net/Amforum/index.php?action=dlattach;topic=42504.0;attach=54688;image


Str.
« Last Edit: February 20, 2019, 0717 UTC by Stretchyman »
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Offline OgreVorbis

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Re: Beginner class D design
« Reply #48 on: February 24, 2019, 1957 UTC »
OK, so I've increased the voltage from 8V up to 18V. Here is what I am getting now:

3MHz 13.8V 4.0A 50W H=5.2W 90.6%
7MHz 13.8V 3.4A 32W H=14.9W 68.2%
3MHz 28.1V 7.5A 200W H=10.7W 94.9%
7MHz 28.1V 6.67A 140W H=47.4W 74.7%
3MHz 48V 14A 640W H=32W 95.2%
7MHz 48V 12.7A 410W H=198W 67.4%

I also briefly tested 5MHz, but my power supply is rated at 600W, so I was really pushing it and didn't get proper measurements.
It made 600W at 5MHz, so clearly it doesn't drop off linearly. It is also possible that my 640W reading it limited by the power supply. I have a 1500W supply on the way.

I have yet to change the core material and that is my next trial. It is amazing how much better it is operating with the 18V.
Despite the success, I still haven't met my goal of 7MHz. Any ideas of other changes I could make? What is usually the weakest link here?
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Offline redhat

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Re: Beginner class D design
« Reply #49 on: February 24, 2019, 2150 UTC »
How are you introducing 'dead time' into the phases of the RF drive?  At 7MHz, you will need about 40% duty cycle on each phase to prevent cross conduction (shoot through).  This could be one of the reasons for the relatively poor efficiency on 7 MHz.

+-RH
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Offline OgreVorbis

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Re: Beginner class D design
« Reply #50 on: February 25, 2019, 1651 UTC »
How are you introducing 'dead time' into the phases of the RF drive?  At 7MHz, you will need about 40% duty cycle on each phase to prevent cross conduction (shoot through).  This could be one of the reasons for the relatively poor efficiency on 7 MHz.

+-RH

I think it is 40% 60%, but I am using a pre-made DDS module (made for this purpose). I checked it on the scope a while back to just see what voltage it was putting out, but I didn't look at duty cycle. I really need to check it again to verify. I am also going to check the outputs of the TC4452 to make sure they're staying square.

So I am having correspondence with a knowledgeable guy via email. He tells me that I should use 20V (in which case I'd have to upgrade to a different driver and change my PCB). Are any of you using the TC4452 or TC44xx on 40 meters? Could the voltage or the driver itself be the problem? My suspicion is the guy is just being nitpicky about the 20V and it doesn't really matter. (As I said earlier, I am using 18V now.)

In addition, I tried changing the cores to type 61 1020. I seem to be getting an erroneous reading from my bird meter now. It says I'm putting out 800W instead of 600W with the old core at 3 MHz even though my power supply is only drawing 700W. At 7MHz the power and the efficiency did not change.
« Last Edit: February 25, 2019, 1700 UTC by OgreVorbis »
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Offline Stretchyman

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Re: Beginner class D design
« Reply #51 on: February 25, 2019, 1738 UTC »
20V won't make any difference, don't waste your time. As stated I've built the same and 15V is fine.

Str.
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Offline redhat

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Re: Beginner class D design
« Reply #52 on: February 25, 2019, 1743 UTC »
I'm using IXDN614 drivers.  The waveforms looked better with these drivers than the '4452's.  15-20V should be fine, I think your bigger problem is the overlap in the PA due to 50% duty cycle drive.

I've also had problems with some RF slugs indicating greater than 100% efficiency when input/output power is calculated.  This is more noticeable with higher power slugs when measuring at less than 75% full scale, as the linearity deteriorates at the lower half of the scale.

+-RH
« Last Edit: February 25, 2019, 1745 UTC by redhat »
Somewhere under the stars...
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Offline Stretchyman

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Re: Beginner class D design
« Reply #53 on: February 25, 2019, 1915 UTC »
Measure power with a calibrated scope probe and some sums (math). I use a 100:1 probe with a BNC T piece, works a treat. Those drivers are rather 'old school' BTW. NCP81074A are way faster. Please read up on the design I pointed towards on amfone. That's the current best one I know.

Str.
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Offline JimIO

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Re: Beginner class D design
« Reply #54 on: February 26, 2019, 0441 UTC »
Maybe OT but could you modulate a class D amp by controlling the duty cycle of the drive?
Does that exist, if so does it have a name?

Offline redhat

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Re: Beginner class D design
« Reply #55 on: February 26, 2019, 0526 UTC »
It is theoretically possible, however, getting conventional devices to switch that fast (100x carrier frequency to achieve 99% modulation) is almost impossible.

+-RH
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Offline OgreVorbis

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Re: Beginner class D design
« Reply #56 on: February 26, 2019, 1959 UTC »
Alright, well I popped two fets, but I learned some things. . .

So I set the 40% 60% duty cycle. It improved a bit (the RF watts went up to 460W from 410W and the efficiency went to 80% up from 74%), so I changed it a bit more and then they popped immediately. I wasn't able to even read the amps. I have to change the duty cycle for each wave individually. Is having them not exactly the same or overlapping a huge problem? I got a new high power current limiting supply, so I'll use that in the future. I am not 100% sure that it was 40 60, but it should be pretty close. My scope doesn't have any fancy stuff. I just had to read the ns/division and do the calculation. I am surprised how little of a change beyond the 40 60 did it.

Anyway, here is the data I gathered:
The DDS exciter is making a decent looking square wave. It has 7ns of rise time regardless of frequency (from 3 to 8 MHz it stays at 7ns). And . . . the drivers have a 20ns rise time (again - regardless of frequency). The fall time on the drivers, does however, seem to get even slightly worse with increased frequency (goes up to like 25ns). So I think the drivers are the culprit. I didn't do the exact math, but I'm thinking 20ns is probably too much for 7 MHz. Is this correct?

If so, then I'm on to making a new PCB. I am going to use the drivers stretchy suggested and put them as close as possible to the fets. I gave the datasheet a quick look and the pinout looks confusing. I am not sure how to hook them up. I addition to the new drivers I am also going to have a custom crystal on the main PCB with an inverter to generate the second wave. It's either going to be the SN74AHCT14N or SN74HC132N for the inverter.
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Offline OgreVorbis

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Re: Beginner class D design
« Reply #57 on: February 26, 2019, 2014 UTC »
How are you introducing 'dead time' into the phases of the RF drive?  At 7MHz, you will need about 40% duty cycle on each phase to prevent cross conduction (shoot through).  This could be one of the reasons for the relatively poor efficiency on 7 MHz.

+-RH

Does that mean 40% on, 60% off, or the opposite? And it's not relative to each other, it is just on time vs off time for each phase individually?
I want to make sure I did this right. I have a feeling I did it backwards.
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Offline redhat

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Re: Beginner class D design
« Reply #58 on: February 26, 2019, 2100 UTC »
40% on, 60% off.  The idea is that the drivers are better at turning the fets on than off, due to miller and reverse transfer capacity in the mosfets.  As such, the duty cycle will be stretched, and if not compensated for, cross conduction occurs in which for a very short time, there is a dead short across the PA voltage source which destroys the transistors.  The way around it is to introduce dead time.  I use the circuit out of a Nautel NX-50 PA module to accomplish this.  The idea is that two drive signals are compared, one normal, and one delayed by a fixed amount.  The two signals are compared, one by NOR, and one by AND.  This produces two signals with a fixed amount of dead time, which prevents cross conduction.  Some experimentation will be necessary to find out what amount of dead time produces best efficiency, but 10-20nS should work.  I believe I used the DS1100z-40 in this application and its working well.

The reason the NCP driver has two output pins is to allow you to tailer the gate resistor values for optimum rise and fall times, usually using a smaller resistor for the low side.

Whenever checking your input drive waveforms, be sure to look at them with a dual channel scope so you can verify that overlap is not occurring (phase A CH1, phase B CH2).



+-RH
« Last Edit: February 26, 2019, 2103 UTC by redhat »
Somewhere under the stars...
WinRadio Excalibur/305 w/ a chi-town resonant loop, Kenwood KDC-U356 for mobile listening.
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Offline Stretchyman

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Re: Beginner class D design
« Reply #59 on: February 28, 2019, 0822 UTC »
Using the NCP drivers which are super fast BTW, I've never bothered with any dead time adjustment and driven the gates directly from both O/P pins, DC coupled with NO RES.

Mind you I have been using the GaN fets, again super fast, but previously used SiC and they were fine only having to use 15V rather than 6V as the driving Vcc.

Again I'd point you toward the article on AMFONE, there's even better FET drivers now with an RF isolated barrier (what next!) but the NCP jobbies are fine.

Str.
'It's better to give than receive' so why RX when you can TX!

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