Ok I looked at the peak drain V and noticed it wasn't as high as class E
That's what I see in simulation and in reality too. CMCD peak drain voltage excursion is less than Class E. In my simplistic back-of-the napkin look, CMCD excursion theoretically shouldn't be a lot more than Vdd but in reality I'm seeing something in the range of 2 to 2.5xVdd, depending upon the tank circuit Q, loading and all that jazz.
I've taken the little beast to my local university where they'll give it their critique. Will be fun for them I think and make a change from LMBA & Doherty at 40+GHz! There's some learned folk there, one quite well know in amplifier design circles. Hopefully they can help me improve it further.
I going to make an educated guess that you're referring to Dr. Steve Cripps at Cardiff U. I took a couple short courses from him a very long time ago. He's a world-renown expert in PA design.
https://www.cardiff.ac.uk/people/view/364356-cripps-steveOh, just to add, I've never seen the need for any duty cycle adjustment and rather crudely just use a dual inverter at the input, inverting once to drive one driver, then inverting again to drive the other. Using a sine wave at the input adjusting it's level from 3V to 5V give a 40-47% adjustment.
Because CMOS/TTL propagation delay for an inverter is ~3-40 nanoseconds, depending upon the family chosen. A 7 MHz signal has a period of ~140 nanoseconds and a half cycle is ~70 ns. With what you have described, you have probably at least 10 nsec propagation delay on one phase (including the FET driver) and so an additional ~5-15 nsec on the other phase, aside from the 180 degree delay. Ten nsec out of 70 nsec is a significant portion of the waveform and apparently enough for you and the settling time of your CMCD circuit. So in this case, leaving it to chance (which totally doesn't surprise me, coming from you) works, but then you probably haven't looked at the rise and fall times on the gates and drains thoroughly over all conditions, multiple DUTs anyway. I like to have options with the ability to adjust for safety margins and maximize the possible conduction angle, hence a non-overlapping clock generator with some adjustability.
So while your crude circuit isn't adjustable, it's still a dual-phase clock generator at least for some range of frequencies but it definitely doesn't lock out/prevent overlapping.
A non-overlapping clock generator isn' t big deal. At it's simplest level, it's a pair of NOR or NAND gates and an inverter in front.
Taken from:
http://individual.utoronto.ca/schreier/lectures/3-6.pdfEdit: Ha. Just realized I know the professor at U Toronto that made these slides. So that's two people I (vaguely) know referred to in one post.