Hellschreiber beacon - with some oomph!

[Charlie_Dont_Surf]

The efficiency is low (if the circuit is actually biased for Class C, I would expect something more like 50-60%) and I have to say that some of that is probably coming from the construction technique. Please don't be offended by this; you've constructed it in a very clean manner. Nice work. It's just that at 7 MHz, there's going to be a fair amount of loss going through all those through-hole components with relatively long leads. A PCB would allow for a more compact circuit with shorter connections between components. Going to SMD would be even better.

[Radiotech]

Will try to make a board with better layout and fewer/shorter leads, but my hands are too big for the SMD stuff sadly.  The board is at least easy to experiment on.

I experimented some with the capacitor that goes from drain to ground on the IRF510, i tried different values, but found that i got the most power without it. Perhaps this is a sign that im operating in C-class. Also removing a few turns from the drain-vcc inductor got me some more power. Almost 3W at 13,8v is pretty ok.

I dont really have any output matching to the 50ohm load, should i try to make a PI network or transformer?


I meassured both Drain-ground(yellow) and Gate-Ground(purple). They seam to be shifted 180 degrees, but i guess that goes for both class C and E. Connecting a probe to the gate of the IRF510 affects output negative.

[redhat]

Something is very wrong if all you can get is ~25% efficiency.  Even my non-optimized CMCD PA's with asymmetrical drive get north of 83% DC-RF efficiency.  Also, keep in mind that all mosfets exhibit a dramatic shift in output capacitance v. Vds.  This can cause tuning problems and a shift in efficiency over the power range, notably on the bottom where voltage excursions are closer to zero.  This can cause a host of problems, among them IPM (incidental phase modulation) which causes problems for complex modulation modes like DRM, and C-QUAM.  This is one of the reasons I try to swamp out the shift in Cds with large tank capacitances.

Per the previous comments; I've seen in my limited experience people go to the ends of the earth to try and optimize a PA, only to get less performance than circuits I tuned empirically.  Usually this is due to circuit strays that are unknown, or unaccounted for in the simulation stage.  This could also be the source of at least some of your difficulty in getting this circuit to behave.

The 180 degree shift is to be expected, as the instant the Vgs exceeds the turn on threshold, the fet will begin to conduct and pull the Vds toward zero.  I would probably explore a different driver for the fet and I imagine some of your efficiency problems will go away.

It should be also noted that measurement accuracy becomes more and more of an issue when measuring the output of these newer higher efficiency PA's.  At some point you have to figure out whose lies you believe.

+-RH

[Radiotech]

I took the advice to try to make the construction a bit more compact, and reduce the leads. With the new circuit i also was able to plan a bit better when placing components.



The low output and efficiency could be due to my circuit not having a bifilar or trifilar transformer, most of the designs out there have one. I dont really understand what they doo, they could provide:

1: Voltage transformation to output more power
2: Antenna impedance matching, to provide more power.

The amplifier from QRPlabs below is one example, but there are many others aswell. I tried this with a bifilar wound 8t T50-43 but got a strange effect where the output started low as 1W and slowly over a couple of seconds rose to 2W. Its possible that i did something wrong with mine, i will try to construct a new one, i need some more materials for it though. The QRP labs amp puts out about 50% efficiency and double the output that mine does, so the bifilar/trifilar transformer is probably importent.



One thing that struck me is that the E-class amplifiers i have seen all seem to use a square wave oscillator signal, and my oscillator has a sinewave signal. Could it be that a square wave signal is needed to go quickly to saturation mode?

[Stretchyman]

Yes the squarewave switching is an essential part of class E. The output device is only ever in 2 states, On or Off, a pure switch. Sinewave puts the output device in a resistive mode between the 2 states, never good..

I have, as have others, posted up schematics with circuit values, just start there, you'll get instant results.

I piddled about for years, simulating and building and testing and modifying and improving.

SMT wise 2012 are quite chunky and suggest you try that size. I too have BIG hands but use a X4 magnifier and have a decent soldering iron. I'm happy with 0805 but can use 0603 but smaller than that (0402) is too small!

I'd stick to PCBs for anything RF. So cheap from CH.

Good you're experimenting and improving....

Simple sim below;

Green is gate (non ideal, realistic slopey squarewave)
Red is output
Blue is drain.

Folk seem hung up on weird idealised circuit values, most of them dont really matter and tuning can be done using toroidal inductors (can vary inductance +/- 50%)


Drain inductor, any old value as long as its 5X or more the Z of the stage (2u is around 80R in this circuit).Any greater is just a waste of wire and more resistance.

C1 is simply adjusted to give (approx) 3.5X the voltage of the supply across the drain, this will vary with FET type as each FET has it's own build in capacitance. Again NOT critical at all.

C2/L2, you can see I've used a standard value rather than some simulated one. IT DOESNT MATTER! The 2 components form a BPF so ANY values will work as long as they are at the correct frequency and this can be adjusted (+/- 50%) by stretching and squeezing the turns to either get the most power or the best efficiency (they dont ever align btw). The BPF is NOT 'on' frequency as has to introduce some lag time wise to align the gate and drain waveforms, they should oppose.

L2 (part)/C3 these actual transform the impedance of the stage from 14R (in this case ) to 50R, it's called a (complex) conjugate match, think of it as SIMPLE match, as it is in physical terms!


That's it, simple eh! You will have to add an LPF and take into account C3 of course.

You can see why the complexity of biasing etc is a waste of time, you want a SWITCHING device NOT a LINEAR one.

Expect 10-15W from this circuit with around 0.8-1.2A of current.

DONT use the 510, USE the 520.




Str

[Radiotech]

I found an error in my datasheet, the efficiency wasnt as bad as i thought 

It turns out that the inductor(8T FT50-43) between drain and VCC impacts the power and efficiency quite a lot! The monofilar had the highest efficiency at 61%, but the trifillar had the highest output in RF-power.


After some tweeking i got nice values

[Radiotech]

Finally i have completed the smaller circuit, and tested it. I lost a bit off efficiency compared to the "test circuit"(2-3% less), but the output power is very nice. At 13,8v i get allmost 10W of output power after the LP-filter. The amplifier maxed out at 21 watt at 24v 

Edit: I managed to increase efficiency to just above 50% by adjusting the bias

[Charlie_Dont_Surf]

It turns out that the inductor(8T FT50-43) between drain and VCC impacts the power and efficiency quite a lot! The monofilar had the highest efficiency at 61%, but the trifillar had the highest output in RF-power.

It does, but only if it is too small.

If it is large enough that XL is sufficiently high then any inductance beyond that has little effect. What is "sufficiently high" you ask? I think that Stretchy's Rule Of Thumb (ROT) of 5x the drain impedance makes sense to me, but I've learned after doing enough of this that at 43 meters for low and moderate power transistors that 2 uH is the minimum sufficient value to avoid any possible issues and get well beyond the range of values where there is a strong effect of L upon the output. I came to this conclusion via simulation and experimentation with real circuits. It is a very clear to see in simulation.

[Charlie_Dont_Surf]

Finally i have completed the smaller circuit, and tested it. I lost a bit off efficiency compared to the "test circuit"(2-3% less), but the output power is very nice. At 13,8v i get allmost 10W of output power after the LP-filter. The amplifier maxed out at 21 watt at 24v 
Edit: I managed to increase efficiency to just above 50% by adjusting the bias

Nice. You have probably reached the point where further time invested will have little effect upon the output power. The simulation that I did yesterday to arrive at my suggested changes to your Class-E circuit (which is very idealized since it does not include parasitic L, C and R) suggests that you will struggle to achieve more than 10 Watts output in Class E (at 12 Volts on the drain), not to mention Class C or whatever it is your circuit is in. Consider 10 Watts (at 12 Volts) to be the "ceiling" of what is possible without some sort of stroke of luck or gift from the parasitic gods.

[Charlie_Dont_Surf]

Also, keep in mind that all mosfets exhibit a dramatic shift in output capacitance v. Vds.  This can cause tuning problems and a shift in efficiency over the power range, notably on the bottom where voltage excursions are closer to zero.  This can cause a host of problems, among them IPM (incidental phase modulation) which causes problems for complex modulation modes like DRM, and C-QUAM.

In my world, we call this "AM to PM" (amplitude modulation to phase modulation), where AM (drain modulation) drives a change in phase.

[Radiotech]

Today i started up the beacon for a test drive, and it worked nicely! I got a clear signal from a web SDR almost 700km away, only using a random wire antenna. I tested it with 10W RF output on 40m(14v supply), TX once a minute, but no issues with temperature. The Arduino controller is mounted on its belly, and i printed out some nice feet for it.

This build was interesting, and i learned a lot about how amplifiers work, and what powers to expect. I also got used to keeping the legs on the components short, and planing the layout better. Thanx for the help and tips i got during the build!

[ChrisSmolinski]

Congrats! Are you going to put this beacon on the air 24/7 ?

[Charlie_Dont_Surf]

Per the previous comments; I've seen in my limited experience people go to the ends of the earth to try and optimize a PA, only to get less performance than circuits I tuned empirically.  Usually this is due to circuit strays that are unknown, or unaccounted for in the simulation stage.

I don't think that this was completely aimed at me but let me be clear.

In the professional world, we can simulate the the PCB, encompassing all the parasitic RLC it presents, and perform full-up EM simulations in software called HFSS or Momentum. It takes time to set up and run but it can be a huge time saver in the long run where it makes sense to do. These models can be crazy accurate up into the GHz range. At the internal chip level, full-up parasitic extraction is employed, taking into account all the layers and all the parasitics they generate, then they do an EM model of the package around the die and roll it all up to get the complete story of how a chip is going to perform. This is invaluable.

As a hobbyist, I'm not going to do an HFSS model for my dumb little FR4 PCB used at 7 MHz.     I spend some time getting things to work well in simulation but, because I am an experienced user, I don't spend a lot of time on it because I know enough to realize that I can't encompass all the parasitic activity. The way I deal with it is what I call the "driving (a car) in deep snow method": target a frequency in simulation above the intended operating frequency, understanding that parasitic activity tends to bring the resonances down in frequency. When you build the actual circuit, it never operates at the the frequency the simulation said it would because of the parasitics. Rather than trying to figure out every little parasitic that causes that, I just offset by how far off from intended the resonance is, make a correction for that offset and then get it to operate close to where I want. Usually this just takes one course correction but sometimes a couple tweaks. I call this "driving in deep snow" because, unless you are traveling in a straight line, you have to pretty much aim the car sort of where you want to go and do course corrections along the way. There won't be precise steering. (Especially in an old rear-wheel drive car with bad tires.   ) For the folks that live in more temperate locations, the analogy would be steering a small boat in choppy water. You aim the boat in a direction and manage through course corrections to get basically where you want to go.

So, if you end up having to tweak the simulated result anyway, the question is, "why bother with simulation at all then?" "Why not just go straight to 'build it and tweak it?' "

Because:
1) Rather than guess, you need a starting point, especially on new circuits. Simulation gives you that starting point and it is a huge time saver to explore possibilities. Knowing that you have a simple method to correct for the inevitable imperfect model gives confidence to explore further.
2) I find that never simulating usually means a hell of a lot more iterations and tweaks to get to where I want.
3) It is worth spending time figuring out some fudge factor frequency offset you need because you may want to use that output network on another board, at another frequency or with a different transistor, etc. Understanding how to reuse that network, the associated PCB layout and what to expect from it saves time in the long run. If you never bother to simulate, you never find out how far off you are and you will make the same mistake again and again.
4) I grew up just building and tweaking stuff until I got it to sort of work the way I wanted. Once I started working professionally in the field, I realized the power of doing a sim first and, for better or worse, now I am totally accustomed to it and can't imagine operating any other way.

[redhat]

Maybe so, and I'll be the first to admit that I can be a stick in the mud.  Its kinda like the old addage, stick with what works.  I've gotten to a level of satisfaction with my current rigs that simulation for me is uneccessary.  It may be true that it would have saved some design time in the beginning getting things to behave, but my methodology seems to work for me most of the time.

I've also seen my share of EE's that couldn't design a hole in the ground.  They would get all wrapped up in modeling something, yet their builds never worked.  You need a good balance of intuition and experience to make things play nice on the first try.

+-RH

[Stretchyman]

You beat me to it, mind you it was yours to do..

I'll + my 10p(c)'s worth.

I started by simulating in LTSpice whilst working for a 3G base station design company in 2005. I had the best engineers in the world to help, scientists too!

Initially started with 160m as the low frequencies mean you can use virtually any FET and wow couldn't believe how simple LTSpice was to use (still free!) and then when construction of the circuit was complete how close the simulation was to the real world.

Of course such a simple program has its shortfalls but you can see waveforms change shape when adjusting circuit values and hence get a 'feel' for what's going on.

Designing a PCB is a piece of cake with even online programs and super cheap manufacturing, highly recommend learning to do this as it's good fun and gives a tidy finish.

Like RH I've done all the simulations I need to do and actually know that the 'idealised' values don't matter at all. The circuit values are published and the circuit works well with off the shelf (not junk box!) modern components.

So you carry on with your simulations mate, we've been there and have done it and are actually doing it whilst you are.....?

Well, what are you doing exactly??

Str.